I spent two days touring Intel’s most advanced fab and talking to its technical leadership to understand what the chips of the future will look like.
A lot of what's coming next – gate-all-around transistors, backside power, CFET, hybrid bonding – is hard to follow without actually seeing it, so we made all the awesome animated explainers that I wish I had while I was prepping.
I also asked Intel’s leadership how the semiconductor industry will cope with the enormous shock in demand from AI.
AI compute has grown 3x a year for the last decade, but according to Intel's CTO, Intel could only double leading-edge wafer production with today’s global stock of chipmaking tools.
What kinds of tricks can foundries pull to extend this crossover point where demand surges way ahead of supply?
This was a totally new format for us - hope you enjoy!
I also made flashcards for the concepts I had to learn to prep for this episode here.
Watch on YouTube; read the transcript.
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Timestamps
(00:00:00) – Intro
(00:00:47) – How Intel brings up a new process node
(00:03:22) – What Intel learned from 10nm
(00:06:28) – From planar transistors to gate-all-around
(00:13:13) – Why High-NA EUV pays off for Intel but not TSMC
(00:19:20) – Could chips have evolved completely differently?
(00:23:33) – Inside Intel’s “Hot Topics” meeting
(00:29:30) – Replacing copper wires with ruthenium
(00:32:41) – Why stacked transistors take a decade to ship
(00:39:45) – Hybrid bonding and the chip-to-chip bottleneck
(00:48:00) – There aren’t enough tools to 10x chip production
(00:53:14) – Can Intel catch up to TSMC?
(01:01:02) – Terafab, and rethinking the fab from scratch
